In various processing architectures, data signals are transferred between circuits operating in different clock domains. In order to ensure that data is properly sampled, the transferred data signals are synchronized to the clock of the receiving domain. Thus, an interface circuit that facilitates the transferring of data from one clock domain to another is known at times as a synchronizer. Without such synchronization, metastability problems produce invalid logic results, which cause digital systems to fail. Metastability arises when the signal input to a flip-flop in a particular clock domain does not meet the set-up or hold time requirements of the flip-flop. As a result, such an input signal places the flip-flop in a metastable state where an output of the flip-flop is momentarily somewhere between a logic level high value and a logic level low value. During the time that the flip-flop is in the metastable state, the flip-flop produces unpredictable logic results that cause system failure. Accordingly, the synchronizer is used to avoid metastability problems in the transferring of data signals between circuits operating in different clock domains.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.